The present invention relates generally to semiconductor device fabrication, and more specifically, to semiconductor devices formed using wafer-to-wafer bonding techniques.
Wafer-to-wafer bonding is a three-dimensional integration and/or packaging process that is typically used to improve packaging size and protect sensitive internal structures of the semiconductor device from environmental influences such as, for example, temperature, moisture, high pressure and oxidizing species. Referring to FIG. 1, a semiconductor device 100 formed according to a conventional wafer-to-wafer bonding processes typically includes a first wafer 102a bonded to a second wafer 102b. The first wafer 102a and the second wafer 102b define an oxide-oxide bonding interface 104 formed therebetween.
Conventional semiconductor devices 100 formed according to conventional wafer-to-wafer bonding processes are susceptible to the formation of uniform cracks 108 in one or more oxide layers 106a/106b defining the oxide-oxide bonding interface 104 (see FIG. 2). In the case of FIG. 2, the crack has been initiated in the process of measuring bond energy by using the well-known Maszara method. The crack length extending along the X-axis from edge towards center can be determined and the bond energy can in turn be determined by inserting a thin blade to initiate a crack form the edge of the bonded wafer pair. The Maszara method describes the relationship of the crack length and bonding energy as:
                              γ          =                                    3              ⁢                              Et                3                            ⁢                              h                2                                                    32              ⁢                                                          ⁢                              L                4                                                    ,                            Equation        ⁢                                  ⁢                  (          1          )                    where, t is the wafer thickness, h is the thickness of the blade, and L the length of the induced crack.
Longer bond cracks suggest a weaker bonding process, which is undesirable. The uniform cracks 108 extend deep into the oxide layer at a distance (d1) and indicate a pulling/peeling separation phenomenon between the opposing oxide layers 106a/106b bonded at the oxide-oxide bonding interface 104. The pulling/peeling separation is typically such that little force is required to separate the two opposing conventional semiconductor wafers 102a/102b at the oxide-oxide bonding interface 104. This can result in delamination and process yield losses during downstream processing with respect to wafer-scale bonding and multistacking.
Conventional methods for improving wafer-to-wafer bonding processes are directed to enhancing the cohesive and adhesive bonding energy of the specific oxide layers 106a/106b that define the oxide-oxide bonding interface 104. For example, various materials having increased toughness have been selected to form the individual oxide layers 106a/106b in an attempt to prevent the formation of uniform cracks. According to other conventional methods, various surface chemistries have been applied to the individual oxide layers 106a/106b in an attempt to strength the oxide material and achieve increase the bonding energy at the oxide-oxide bonding interface 104.